公开(公告)号：US20240111531A1

公开(公告)日：2024-04-04

申请号：US18369082

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Stephen T. PALERMO ,  Srihari MAKINENI ,  Shubha BOMMALINGAIAHNAPALLYA ,  Neelam CHANDWANI ,  Rany T. ELSAYED ,  Udayan MUKHERJEE ,  Lokpraveen MOSUR ,  Adwait PURANDARE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US20170148728A1

公开(公告)日：2017-05-25

申请号：US15125964

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Silvio E. BOU-GHAZALE ,  Rany T. ELSAYED ,  Niti GOEL

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L27/0733 ,  H01L28/88 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.