公开(公告)号：US20250076954A1

公开(公告)日：2025-03-06

申请号：US18883276

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Vivek GARG ,  Ankush VARMA ,  Krishnakanth SISTLA ,  Nikhil GUPTA ,  Nikethan Shivanand BALIGAR ,  Stephen WANG ,  Nilanjan PALIT ,  Timothy Yee-Kwong KAM ,  Adwait PURANDARE ,  Ujjwal GUPTA ,  Stanley CHEN ,  Dorit SHAPIRA ,  Shruthi VENUGOPAL ,  Suresh CHEMUDUPATI ,  Rupal PARIKH ,  Eric DEHAEMER ,  Pavithra SAMPATH ,  Phani Kumar KANDULA ,  Yogesh BANSAL ,  Dean MULLA ,  Michael TULANOWSKI ,  Stephen Paul HAAKE ,  Andrew HERDRICH ,  Ripan DAS ,  Nazar Syed HAIDER ,  Aman SEWANI

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20240111531A1

公开(公告)日：2024-04-04

申请号：US18369082

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Stephen T. PALERMO ,  Srihari MAKINENI ,  Shubha BOMMALINGAIAHNAPALLYA ,  Neelam CHANDWANI ,  Rany T. ELSAYED ,  Udayan MUKHERJEE ,  Lokpraveen MOSUR ,  Adwait PURANDARE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US20220413591A1

公开(公告)日：2022-12-29

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. SHAH ,  Suresh CHEMUDUPATI ,  Alexander GENDLER ,  David HUNT ,  Christopher M. MACNAMARA ,  Ofer NATHAN ,  Adwait PURANDARE ,  Ankush VARMA

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.