公开(公告)号：US20190042456A1

公开(公告)日：2019-02-07

申请号：US16021319

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Yakov Evgeni Ginzburg ,  Naru Dames Sundar ,  Chih-Jen Chang ,  Amir Keren ,  Ravi Tangirala

IPC: G06F12/0893 ,  G06F12/084 ,  G06F12/1018 ,  G06F9/455

Abstract: There is disclosed in one example a computing system, including: a processor including one or more computing cores; a cache having n discrete cache banks of the same cache level; and a cache controller including n discrete cache buses to communicatively couple the cache controller to the cache, wherein the cache buses are of width b, and a cache access controller configured to: receive an access request for an object of size s, wherein s>b; divide the object into k chunks of size b or smaller; and transfer the object to or from the cache in one or more iterations, the iterations including transferring n chunks of size b or smaller in parallel via the cache buses.