公开(公告)号：US20210175238A1

公开(公告)日：2021-06-10

申请号：US17155015

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Brain S. DOYLE ,  Kaan OGUZ ,  Ricky J. TSENG ,  Kevin P. O'BRIEN

IPC: H01L27/1159 ,  H01L29/66 ,  H01L29/78 ,  G11C5/06

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.