公开(公告)号：US10896141B2

公开(公告)日：2021-01-19

申请号：US16364725

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Jeffrey J. Cook ,  Jonathan D. Pearce ,  Srikanth T. Srinivasan ,  Rishiraj A. Bheda ,  David B. Sheffield ,  Abhijit Davare ,  Anton Alexandrovich Sorokin

IPC: G06F13/16 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0815

Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.

公开(公告)号：US20200310992A1

公开(公告)日：2020-10-01

申请号：US16364725

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Jeffrey J. Cook ,  Jonathan D. Pearce ,  Srikanth T. Srinivasan ,  Rishiraj A. Bheda ,  David B. Sheffield ,  Abhijit Davare ,  Anton Alexandrovich Sorokin

IPC: G06F13/16 ,  G06F9/38 ,  G06F12/0815 ,  H04L9/06

Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.