公开(公告)号：US12197887B2

公开(公告)日：2025-01-14

申请号：US16818889

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/483 ,  G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.

公开(公告)号：US20240126506A1

公开(公告)日：2024-04-18

申请号：US18399381

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/483 ,  G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F17/16

CPC classification number: G06F7/485 ,  G06F7/483 ,  G06F7/4876 ,  G06F7/49947 ,  G06F7/5443 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.

公开(公告)号：US20200218508A1

公开(公告)日：2020-07-09

申请号：US16818889

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Roberto DiCecco ,  Joshua Fender ,  Shane O'Connell

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/544 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.