公开(公告)号：US12073227B2

公开(公告)日：2024-08-27

申请号：US17131547

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Noor Mubeen ,  Ashraf H. Wadaa ,  Andrey Gabdulin ,  Russell Fenger ,  Deepak Samuel Kirubakaran ,  Marc Torrant ,  Ryan Thompson ,  Georgina Saborio Dobles ,  Lingjing Zeng

IPC: G06F9/4401 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/4405 ,  G06F9/3877 ,  G06F9/4403 ,  G06F9/5094

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

公开(公告)号：US20220058029A1

公开(公告)日：2022-02-24

申请号：US17131547

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Noor Mubeen ,  Ashraf H. Wadaa ,  Andrey Gabdulin ,  Russell Fenger ,  Deepak Samuel Kirubakaran ,  Marc Torrant ,  Ryan Thompson ,  Georgina Saborio Dobles ,  Lingjing Zeng

IPC: G06F9/4401 ,  G06F9/50 ,  G06F9/38

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.