公开(公告)号：US20220091851A1

公开(公告)日：2022-03-24

申请号：US17029335

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  ALAA ALAMELDEEN ,  ABHISHEK BASAK ,  SCOTT CONSTABLE ,  FRANCIS MCKEEN ,  JOSEPH NUZMAN ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  XIANG ZOU

IPC: G06F9/38 ,  G06F9/48 ,  G06F21/54 ,  G06F9/30

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (μop) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing μop. Other embodiments are described and claimed.

公开(公告)号：US20220207187A1

公开(公告)日：2022-06-30

申请号：US17134320

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： SCOTT CONSTABLE ,  MARK SHANAHAN ,  MONA VIJ ,  BIN XING ,  KRYSTOF ZMUDZINSKI

IPC: G06F21/75

Abstract: Systems, methods, and apparatuses relating to an instruction that allows a trusted execution environment to react to an asynchronous exit are described. In one embodiment, a hardware processor includes a register comprising a field, that when set, is to enable an architecturally protected execution environment for code in an architecturally protected enclave in memory, a decoder circuit to decode a single instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to invoke a handler to handle an asynchronous exit from execution of the code in the architecturally protected enclave and then resume execution of the code in the architecturally protected enclave from where the asynchronous exit occurred, and the execution circuit to respond to the decoded instruction as specified by the opcode.