公开(公告)号：US20200243655A1

公开(公告)日：2020-07-30

申请号：US16260600

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Said RAMI ,  Hyung-Jin LEE ,  Surej RAVIKUMAR ,  Kinyip PHOA

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/12 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

公开(公告)号：US20240006347A1

公开(公告)日：2024-01-04

申请号：US17853572

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Qiang YU ,  Georgios C. DOGIAMIS ,  Gwang-Soo KIM ,  Ibukunoluwa MOMSON ,  Ali FARID ,  Said RAMI

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/585 ,  H01L24/16 ,  H01L23/5226 ,  H01L2224/16145

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to fabricating passive circuits on a surface of a BEOL of a package, for example on a C4 connection layer of the BEOL. In embodiments, the passive circuits may be fabricated using a standard bump process. Other embodiments may be described and/or claimed.