-
公开(公告)号：US20230062668A1
公开(公告)日：2023-03-02
申请号：US17411899
申请日：2021-08-25
Applicant: Intel Corporation
Inventor： Naveen Vittal Prabhu , Aliasgar Madraswala , Sandeep Rasoori , Trupti Bemalkhedkar
IPC: G06F3/06
Abstract: Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.
Search Results
1
records
(took 0.009 seconds)
筛选
AND
AND
过滤
NOT
NOT
Scan to Join
