公开(公告)号：US20230086751A1

公开(公告)日：2023-03-23

申请号：US17483279

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Aliasgar Madraswala ,  Pranav Chava

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/30 ,  G11C16/08

Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

公开(公告)号：US12154627B2

公开(公告)日：2024-11-26

申请号：US17483279

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Aliasgar Madraswala ,  Pranav Chava

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/30

Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

公开(公告)号：US20190043567A1

公开(公告)日：2019-02-07

申请号：US16115372

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Shantanu Rajwade ,  Rohit Shenoy ,  Aliasgar Madraswala ,  Pranav Kalavade

IPC: G11C11/56 ,  G11C16/26 ,  H01L23/00 ,  G06F3/06

Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.

公开(公告)号：US09740419B2

公开(公告)日：2017-08-22

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US20190180829A1

公开(公告)日：2019-06-13

申请号：US16276695

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Lei Chen ,  Xin Guo ,  Ali Khakifirooz ,  Aliasgar Madraswala ,  Yogesh B. Wakchaure

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/22 ,  G06F11/07

Abstract: An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

公开(公告)号：US20170139626A1

公开(公告)日：2017-05-18

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US09570159B1

公开(公告)日：2017-02-14

申请号：US14884428

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G11C11/56 ,  G11C11/4096 ,  G11C16/22 ,  G11C7/10

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell.

Abstract translation: 公开了在功率损耗事件期间保存固态驱动器的数据的方法，装置，系统和制品。 一种示例性方法包括在从固态驱动器的处理器检测到功率损耗事件时发送中止正在进行的中止的存储器单元的写入操作的命令。 响应于正在进行的写入操作被中止的指示，将要被写入被中止的存储单元的数据被恢复。 要写入中止的存储单元的数据的第一部分被写入第一存储器单元。 要写入中止的存储单元的数据的第二部分被写入第二存储单元。

公开(公告)号：US20240354209A1

公开(公告)日：2024-10-24

申请号：US18762492

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/20 ,  G06F1/30 ,  G06F11/16 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US12099420B2

公开(公告)日：2024-09-24

申请号：US17133834

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/16 ,  G06F11/20 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US20230062668A1

公开(公告)日：2023-03-02

申请号：US17411899

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Sandeep Rasoori ,  Trupti Bemalkhedkar

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.