公开(公告)号：US20220337292A1

公开(公告)日：2022-10-20

申请号：US17763209

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Sanket JAIN ,  Benjamin JANN ,  Ashoke RAVI ,  Satwik PATNAIK

IPC: H04B7/0413 ,  H04B7/26 ,  H04B7/01

Abstract: A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.