公开(公告)号：US20200293696A1

公开(公告)日：2020-09-17

申请号：US16885726

申请日：2020-05-28

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Santhosh Kumar Vanaparthy

IPC: G06F21/79 ,  G06F3/06 ,  H04L9/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to generate a pseudo-random sequence of bits, permute one or more bits of binary unscrambled data, and generate scrambled data based on an exclusive-or operation between the pseudo-random sequence of bits and the permuted data. Other embodiments are disclosed and claimed.

公开(公告)号：US12032725B2

公开(公告)日：2024-07-09

申请号：US16885726

申请日：2020-05-28

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Santhosh Kumar Vanaparthy

IPC: G06F21/79 ,  G06F3/06 ,  H04L9/06

CPC classification number: G06F21/79 ,  G06F3/0623 ,  G06F3/0661 ,  G06F3/0679 ,  H04L9/0631 ,  H04L9/0656 ,  H04L2209/04

Abstract: Techniques and mechanisms to provide one or more substrates, and logic coupled to the one or more substrates. In an embodiment, the logic is to generate a pseudo-random sequence of bits, and to permute one or more bits of binary unscrambled data. In another embodiment, the logic is further to generate scrambled data based on an exclusive-or operation between the pseudo-random sequence of bits and the permuted data.