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公开(公告)号：US20190245679A1
公开(公告)日：2019-08-08
申请号：US15887290
申请日：2018-02-02
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Matthew , Sudhir K. Satpathy , Vinodh Gopal
Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X−1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.
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