公开(公告)号：US20190165270A1

公开(公告)日：2019-05-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Sarah E. ATANASOV ,  Kevin P. O'BRIEN ,  Robert L. BRISTOL

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.