DIFFERENTIAL HARDMASKS FOR MODULATION OF ELECTROBUCKET SENSITIVITY

    公开(公告)号:US20190318959A1

    公开(公告)日:2019-10-17

    申请号:US16346305

    申请日:2016-12-23

    申请人: Intel Corporation

    摘要: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

    METAL OXYCARBIDE RESISTS AS LEAVE BEHIND PLUGS

    公开(公告)号:US20200335434A1

    公开(公告)日:2020-10-22

    申请号:US16389672

    申请日:2019-04-19

    申请人: Intel Corporation

    摘要: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

    PHOTOBUCKET FLOOR COLORS WITH SELECTIVE GRAFTING

    公开(公告)号:US20190318958A1

    公开(公告)日:2019-10-17

    申请号:US16317015

    申请日:2016-09-30

    申请人: Intel Corporation

    摘要: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

    DIFFERENTIAL HARDMASKS FOR MODULATION OF ELECTROBUCKET SENSITIVITY

    公开(公告)号:US20220130719A1

    公开(公告)日:2022-04-28

    申请号:US17568648

    申请日:2022-01-04

    申请人: Intel Corporation

    摘要: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.