公开(公告)号：US12248696B2

公开(公告)日：2025-03-11

申请号：US17340866

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Saurabh Jain ,  Srivatsa Rangachar Srinivasa ,  Akshay Krishna Ramanathan ,  Gurpreet Singh Kalsi ,  Kamlesh R. Pillai ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F7/523

Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

公开(公告)号：US20220113974A1

公开(公告)日：2022-04-14

申请号：US17561029

申请日：2021-12-23

Applicant: INTEL CORPORATION

Inventor： Om Ji Omer ,  Gurpreet Singh Kalsi ,  Anirud Thyagharajan ,  Saurabh Jain ,  Kamlesh R. Pillai ,  Sreenivas Subramoney ,  Avishaii Abuhatzera

IPC: G06F9/38 ,  G06F9/30

Abstract: A memory architecture includes processing circuits co-located with memory subarrays for performing computations within the memory architecture. The memory architecture includes a plurality of decoders in hierarchical levels that include a multicast capability for distributing data or compute operations to individual subarrays. The multicast may be configurable with respect to individual fan-outs at each hierarchical level. A computation workflow may be organized into a compute supertile representing one or more “supertiles” of input data to be processed in the compute supertile. The individual data tiles of the input data supertile may be used by multiple compute tiles executed by the processing circuits of the subarrays, and the data tiles multicast to the respective processing circuits for efficient data loading and parallel computation.

公开(公告)号：US11949414B2

公开(公告)日：2024-04-02

申请号：US17131215

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Akshay Krishna Ramanathan ,  Kamlesh Pillai ,  Sreenivas Subramoney ,  Srivatsa Rangachar Srinivasa ,  Anirud Thyagharajan ,  Om Ji Omer ,  Saurabh Jain

IPC: H03K19/17728 ,  H03K19/1776

CPC classification number: H03K19/17728 ,  H03K19/1776

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve in-memory multiply and accumulate operations. An example apparatus includes a first multiplexer in a subarray of memory, the first multiplexer to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers and return second values from an intersection of a row and the column of the LUT based on a first element of a first operand; shift and adder logic in the subarray, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and accumulation storage in the subarray, the accumulation storage to store at least the shifted second values.

公开(公告)号：US20210111722A1

公开(公告)日：2021-04-15

申请号：US17131215

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Akshay Krishna Ramanathan ,  Kamlesh Pillai ,  Sreenivas Subramoney ,  Srivatsa Rangachar Srinivasa ,  Anirud Thyagharajan ,  Om Ji Omer ,  Saurabh Jain

IPC: H03K19/17728 ,  H03K19/1776

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve in-memory multiply and accumulate operations. An example apparatus includes a first multiplexer in a subarray of memory, the first multiplexer to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers and return second values from an intersection of a row and the column of the LUT based on a first element of a first operand; shift and adder logic in the subarray, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and accumulation storage in the subarray, the accumulation storage to store at least the shifted second values.