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公开(公告)号:US20190042252A1
公开(公告)日:2019-02-07
申请号:US16147691
申请日:2018-09-29
Applicant: Intel Corporation
Inventor: Himanshu Kaul , Mark Anders , Seongjong Kim
Abstract: A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An embodiment includes M slices, each of which calculates the vector dot products between a corresponding segment of the first and the second N-bit vectors. Each of the slices outputs intermediary multiplier results for the lower precision modes, but not for highest precision mode. A plurality of adder trees to sum up the plurality of intermediate multiplier results, with each adder tree producing a respective adder out result. An accumulator to merge the adder out result from a first adder tree with the adder out result from a second adder tree to produce the vector dot product of the first and the second N-bit vector in the highest precision mode.