公开(公告)号：US09489720B2

公开(公告)日：2016-11-08

申请号：US14494163

申请日：2014-09-23

Applicant: Intel Corporation

Inventor： Shaul Oron ,  Gilad Michael

IPC: G06T5/00 ,  G06T7/40 ,  G06T5/20

CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T7/40

Abstract: System, apparatus, method, and computer readable media for texture enhanced non-local means (NLM) image denoising. In embodiments, detail is preserved in filtered image data through a blending between the noisy input target pixel value and the NLM pixel value that is driven by self-similarity and further informed by an independent measure of local texture. In embodiments, the blending is driven by one or more blending weight or coefficient that is indicative of texture so that the level of detail preserved by the enhanced noise reduction filter scales with the amount of texture. Embodiments herein may thereby denoise regions of an image that lack significant texture (i.e. are smooth) more aggressively than more highly textured regions. In further embodiments, the blending coefficient is further determined based on similarity scores of candidate patches with the number of those scores considered being based on the texture score.

Abstract translation: 用于纹理增强的非本地装置（NLM）图像去噪的系统，装置，方法和计算机可读介质。 在实施例中，通过在噪声输入目标像素值和由自相似性驱动的NLM像素值之间进行混合，并通过局部纹理的独立测量进一步通知，滤波图像数据中的细节被保留。 在实施例中，混合由指示纹理的一个或多个混合权重或系数驱动，使得由增强噪声降低滤波器保留的细节水平随纹理量而变化。 因此，这里的实施例可以比较高纹理化区域更积极地去除缺乏显着纹理（即平滑）的图像区域。 在另外的实施例中，基于候选补片的相似性得分进一步确定混合系数，其中考虑的那些分数的数量基于纹理得分。

公开(公告)号：US09678749B2

公开(公告)日：2017-06-13

申请号：US14578605

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shaul Oron ,  Gilad Michael

IPC: G06F7/53 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3001 ,  G06F7/5306 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/3017 ,  G06F9/3822 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/455 ,  G06F9/4552

Abstract: A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes logic identify a multiplication instruction to multiply a first number and a second number. The execution unit includes logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters. The SSM includes logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products. The SSM also includes logic to sum the partial products to yield a result of the multiplication instruction.

公开(公告)号：US20160179514A1

公开(公告)日：2016-06-23

申请号：US14578605

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Shaul Oron ,  Gilad Michael

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F7/5306 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/3017 ,  G06F9/3822 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/455 ,  G06F9/4552

Abstract: A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes logic identify a multiplication instruction to multiply a first number and a second number. The execution unit includes logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters. The SSM includes logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products. The SSM also includes logic to sum the partial products to yield a result of the multiplication instruction.

Abstract translation: 处理器包括前端，包括解码器，包括移位和乘法器（SSM）的执行单元和退出单元。 解码器包括逻辑，识别乘法指令以乘以第一数和第二数。 执行单元包括基于指令访问基于第二数目的查找表以确定多个移位参数和一个或多个标志参数的逻辑。 SSM包括使用移位参数来移动第一数字以确定多个部分乘积的逻辑，以及用于确定部分乘积的符号的标志参数的逻辑。 SSM还包括对部分乘积求和以产生乘法指令的结果的逻辑。