公开(公告)号：US20230016817A1

公开(公告)日：2023-01-19

申请号：US17359529

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Shavindra PREMARATNE ,  Albert SCHMITZ ,  Anne MATSUURA ,  Xiang ZOU

IPC: G06N10/00 ,  G06F11/14 ,  H03K19/003

Abstract: Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.

公开(公告)号：US20240193451A1

公开(公告)日：2024-06-13

申请号：US18078781

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Anne MATSUURA ,  Pradnya Laxman KHALATE ,  Shavindra PREMARATNE ,  Sahar DARAEIZADEH ,  Albert SCHMITZ ,  Xin-Chuan WU ,  Todor MLADENOV ,  Brandon BARNETT

IPC: G06N10/20

CPC classification number: G06N10/20

Abstract: Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of an apparatus comprises: a host processor to perform a partial compilation on hybrid quantum-classical source code to generate one or more sequential blocks of quantum operations; a quantum compiler accelerator to receive compilation work offloaded by the host processor including the one or more sequential blocks of quantum operations, the quantum compiler to perform optimization operations to optimize runtime execution of one or more of the quantum operations in view if a quantum accelerator architecture to generate optimized quantum operations; and a quantum execution accelerator having the quantum accelerator architecture to execute the optimized quantum operations to manipulate a state of one or more qubits, to measure a state of the one or more qubits, and to provide measurement data indicating the state to the host processor.