公开(公告)号：US20240169094A1

公开(公告)日：2024-05-23

申请号：US17993634

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Jerome Anand ,  Anil Kumar Bangalore Rajashekar ,  Dinkar Dhawale ,  Sachin P. Kamat ,  Shidlingeshwar Khatakalle ,  Mitul Shah

IPC: G06F21/62

CPC classification number: G06F21/6254

Abstract: Protecting data privacy in a federated learning computing environment includes receiving a model trained by a federated server with public data using global model parameters, getting local shareable data from a local shareable database, training the model with the local shareable data using the global model parameters to generate local model parameters, and obscuring the local model parameters. Protecting data privacy includes sending the local model parameters to the federated server, modifying the model to classify private data, and training the model with the private data using the local model parameters and updating the local model parameters.

公开(公告)号：US20240111598A1

公开(公告)日：2024-04-04

申请号：US17957919

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Shidlingeshwar Khatakalle ,  Vijay Anand Mathiyalagan ,  Diyanesh Babu Chinnakkonda Vidyapoornachary

IPC: G06F9/50

CPC classification number: G06F9/505

Abstract: In an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. The sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.

公开(公告)号：US20230137769A1

公开(公告)日：2023-05-04

申请号：US17518186

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Stephen H. Gunther ,  Shidlingeshwar Khatakalle ,  Diyanesh Babu Chinnakkonda Vidyapoornachary

IPC: G06F9/50

Abstract: Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.