公开(公告)号：US20220199142A1

公开(公告)日：2022-06-23

申请号：US17131585

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Sambaran Mitra

IPC: G11C11/4074 ,  G11C11/4096 ,  G06F11/10

Abstract: Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.

公开(公告)号：US20210132123A1

公开(公告)日：2021-05-06

申请号：US17128070

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Stephen Gunther

IPC: G01R19/25

Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.

公开(公告)号：US12117469B2

公开(公告)日：2024-10-15

申请号：US17128070

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Stephen Gunther

IPC: G01R19/25 ,  H02J4/00

CPC classification number: G01R19/2513 ,  H02J4/00

Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.

公开(公告)号：US20240183884A1

公开(公告)日：2024-06-06

申请号：US18076352

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Vikrant Thigle ,  Vijay Anand Mathiyalagan ,  Anand Haridass ,  Arun Chandrasekhar ,  Gerald Pasdast

IPC: G01R19/00 ,  G01R19/25 ,  G05F1/46

CPC classification number: G01R19/0038 ,  G01R19/25 ,  G05F1/46

Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.

公开(公告)号：US20240111598A1

公开(公告)日：2024-04-04

申请号：US17957919

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Shidlingeshwar Khatakalle ,  Vijay Anand Mathiyalagan ,  Diyanesh Babu Chinnakkonda Vidyapoornachary

IPC: G06F9/50

CPC classification number: G06F9/505

Abstract: In an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. The sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.

公开(公告)号：US20230137769A1

公开(公告)日：2023-05-04

申请号：US17518186

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Stephen H. Gunther ,  Shidlingeshwar Khatakalle ,  Diyanesh Babu Chinnakkonda Vidyapoornachary

IPC: G06F9/50

Abstract: Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.

公开(公告)号：US20220404883A1

公开(公告)日：2022-12-22

申请号：US17354736

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Vijay Anand Mathiyalagan ,  Madhusudan Chidambaram

IPC: G06F1/26 ,  G05F1/10 ,  H04L12/26 ,  H04L12/24

Abstract: Various embodiments provide apparatuses, systems, and methods for bandwidth-based control of phase count in a voltage regulator. The techniques described herein may be used with a voltage regulator that supply power to a data circuit that processes data traffic. The voltage regulator includes a plurality of phases to generate an output voltage that is provided to the data circuit. A control circuit determines a bandwidth of the data traffic that is handled by the data circuit and control a number of the phases that are active based on the determined bandwidth. Other embodiments may be described and claimed.