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公开(公告)号:US20220308877A1
公开(公告)日:2022-09-29
申请号:US17213874
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Subramaniam MAIYURAN , Sudarshanram SHETTY , Travis SCHLUESSLER , Guei-Yuan LUEH , PingHang CHEUNG , Srividya KARUMURI , Chandra S. GURRAM , Shuai MU , Vikranth VEMULAPALLI
IPC: G06F9/30 , G06F9/38 , G06F12/0837
Abstract: A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.
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公开(公告)号:US20220066737A1
公开(公告)日:2022-03-03
申请号:US17003334
申请日:2020-08-26
Applicant: Intel Corporation
Inventor: Shuai MU , Cristina S. ANDERSON , Subramaniam MAIYURAN
Abstract: Examples described herein relate to instructions to request performance of tanh and sigmoid instructions. For example, a compiler can generate native tanh instructions to perform tanh. In some examples, a tanh function can be compiled into instructions that include an instruction to perform either tanh(input) or tanh(input)/input depending on a value of the input to generate an intermediate output; an instruction to cause a performance of generation of scale factor based on the input; and an instruction to cause performance of a multiplication operation on the intermediate result with the scale factor. For example, a sigmoid function can be compiled to cause a math pipeline to perform a range check and performs operations based on a range.
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