公开(公告)号：US20210012553A1

公开(公告)日：2021-01-14

申请号：US17032964

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Michael APODACA ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Timothy ROWLEY ,  Joshua BARCZAK ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20220308877A1

公开(公告)日：2022-09-29

申请号：US17213874

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam MAIYURAN ,  Sudarshanram SHETTY ,  Travis SCHLUESSLER ,  Guei-Yuan LUEH ,  PingHang CHEUNG ,  Srividya KARUMURI ,  Chandra S. GURRAM ,  Shuai MU ,  Vikranth VEMULAPALLI

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0837

Abstract: A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

公开(公告)号：US20240013470A1

公开(公告)日：2024-01-11

申请号：US18371614

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20220414970A1

公开(公告)日：2022-12-29

申请号：US17868618

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20220180588A1

公开(公告)日：2022-06-09

申请号：US17113944

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Travis SCHLUESSLER ,  William B. DAVIDSON ,  Abhishek VENKATESH

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20

Abstract: A memory local to a graphics execution unit stores a shareable resource that has a constant value across different instances of an application. The system can include a shared resource manager to identify resources of an application as static resources. For multiple instances of the application executed on the graphics execution unit, the shared resource manager makes the static resource shareable among the multiple instances of the application, and maps the static resource to the multiple instances for runtime execution. The graphic execution unit executes the multiple instances of the application.

公开(公告)号：US20200211265A1

公开(公告)日：2020-07-02

申请号：US16236218

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carson BROWNLEE ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Philip LAWS ,  Thomas RAOUX ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06T15/00

Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.

公开(公告)号：US20240046403A1

公开(公告)日：2024-02-08

申请号：US18231379

申请日：2023-08-08

Applicant: Intel Corporation

Inventor： Michael DOYLE ,  Travis SCHLUESSLER ,  Gabor LIKTOR ,  Atsuo KUWAHARA ,  Jefferson AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F16/9027 ,  G06F9/3877 ,  G06F9/3891 ,  G06F9/5077 ,  G06T15/005 ,  G06T15/06

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20230162428A1

公开(公告)日：2023-05-25

申请号：US17982766

申请日：2022-11-08

Applicant: INTEL CORPORATION

Inventor： Michael APODACA ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Timothy ROWLEY ,  Joshua BARCZAK ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38

CPC classification number: G06T15/06 ,  G06F16/9027 ,  G06F7/14 ,  G06F9/3877 ,  G06N3/02

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20230161576A1

公开(公告)日：2023-05-25

申请号：US17535383

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Travis SCHLUESSLER

IPC: G06F8/41

CPC classification number: G06F8/4441

Abstract: Examples described herein relate to technologies to execute a compiler for a process to be executed by one or more graphics processing units (GPUs) to compile the process based on run-time profile guided optimization (PGO). In some examples, the process is compiled based on run-time PGO is based on profile data versioned by application, driver, and GPU version; previously generated profile data; a subset of draws to profile and optimize; or other factors.

公开(公告)号：US20210287419A1

公开(公告)日：2021-09-16

申请号：US17159399

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.