公开(公告)号：US20220365869A1

公开(公告)日：2022-11-17

申请号：US17456583

申请日：2021-11-25

Applicant: Intel Corporation

Inventor： Subinlal PK ,  Keith JONES ,  Rolf KUEHNIS

IPC: G06F11/36

Abstract: A debug test system is provided. The debug test system includes one or more interfaces configured to communicate with a target system and processing circuitry configured to control the one or more interfaces. Further, the processing circuitry is configured to receive information about an operation state of the target system from the target system and to generate control information for the target system to adjust a debug session on the target system. The processing circuitry is further configured to transmit the control information to the target system.