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1.发明申请公开(公告)号：US20160095209A1
公开(公告)日：2016-03-31
申请号：US14498958
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Robert STARKSTON , John GUZEK , Patrick NARDI , Keith JONES , Javier SOTO GONZALEZ
CPC classification number: H05K1/0271 , H01L23/16 , H01L23/49833 , H01L23/562 , H01L24/97 , H01L2224/16225 , H01L2924/15311 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K2201/09136 , H05K2201/10977 , H05K2201/2009
Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.
Abstract translation: 公开了用于形成具有集成的加强件的封装衬底的技术。 提供了一组封装基板。 然后在封装衬底面板的每个封装衬底上形成粘附层。 然后，通过粘合层将一块扶强材板附接到封装基板的面板，每个加强件对应于相应的封装基板。 然后将封装衬底的面板分成具有集成的加强件的单个封装衬底。 单个封装衬底上的加强件包括延伸到封装衬底的边缘的突片。
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公开(公告)号：US20220365869A1
公开(公告)日：2022-11-17
申请号：US17456583
申请日：2021-11-25
Applicant: Intel Corporation
Inventor： Subinlal PK , Keith JONES , Rolf KUEHNIS
IPC: G06F11/36
Abstract: A debug test system is provided. The debug test system includes one or more interfaces configured to communicate with a target system and processing circuitry configured to control the one or more interfaces. Further, the processing circuitry is configured to receive information about an operation state of the target system from the target system and to generate control information for the target system to adjust a debug session on the target system. The processing circuitry is further configured to transmit the control information to the target system.
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