公开(公告)号：US20220100500A1

公开(公告)日：2022-03-31

申请号：US17033649

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas MADAELIL ,  Jonathan COMBS ,  Vikash AGARWAL

IPC: G06F9/22 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described. In one embodiment, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, a fetch circuit to fetch a first block of instructions and send the first block of instructions to the first decode cluster for decoding, and fetch a second block of instructions younger in program order than the first block of instructions and send the second block of instructions to the second decode cluster for decoding, a microcode sequencer comprising a memory that stores a plurality of micro-operations, and an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.

公开(公告)号：US20220100516A1

公开(公告)日：2022-03-31

申请号：US17033680

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Thomas MADAELIL ,  Jonathan COMBS ,  Khary ALEXANDER ,  Martin LICHT ,  Vikash AGARWAL

IPC: G06F9/30 ,  G06F12/0875

Abstract: Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, an instruction cache, an instruction length decoder circuit, a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as an end boundary of a variable length instruction, an incomplete decode table comprising a bit, for each proper subset of sections of instruction data, that indicates when that proper subset of sections has one or more invalid predecode bits in the predecode cache; and a fetch circuit to, for an incoming address of instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the instruction cache for the instruction data at the incoming address and a hit in the incomplete decode table that indicates a proper subset of sections of the instruction data for the incoming address has one or more invalid predecode bits in the predecode cache, causes the instruction length decoder circuit to generate one or more predecode bits for the proper subset of sections of the instruction data for the incoming address that has the one or more invalid predecode bits.