公开(公告)号：US20190267062A1

公开(公告)日：2019-08-29

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

公开(公告)号：US10714163B2

公开(公告)日：2020-07-14

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.