公开(公告)号：US20240296140A1

公开(公告)日：2024-09-05

申请号：US18662621

申请日：2024-05-13

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F13/1631 ,  G06F13/1673 ,  G06F13/4004

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US11658159B2

公开(公告)日：2023-05-23

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: G11C11/00 ,  H01L25/065 ,  G11C5/02 ,  G06F12/10

CPC classification number: H01L25/0657 ,  G06F12/10 ,  G11C5/025 ,  G06F2212/657 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US10714163B2

公开(公告)日：2020-07-14

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

公开(公告)号：US11188255B2

公开(公告)日：2021-11-30

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00 ,  G06F13/28

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

公开(公告)号：US20190303039A1

公开(公告)日：2019-10-03

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F3/06 ,  G06F13/16

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

公开(公告)号：US20190267062A1

公开(公告)日：2019-08-29

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

公开(公告)号：US11580054B2

公开(公告)日：2023-02-14

申请号：US16235608

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/40 ,  G06F13/16

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US20220013505A1

公开(公告)日：2022-01-13

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: H01L25/065 ,  G11C5/02 ,  G06F12/10

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US20210151120A1

公开(公告)日：2021-05-20

申请号：US17133810

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Hwa Chaw Law ,  Yu Ying Ong

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/00

Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

公开(公告)号：US12094551B2

公开(公告)日：2024-09-17

申请号：US17133810

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Hwa Chaw Law ,  Yu Ying Ong

IPC: G11C29/42 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/44 ,  G11C29/78

Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.