公开(公告)号：US20190215146A1

公开(公告)日：2019-07-11

申请号：US15868907

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Yanjing Ke ,  Dinesh Patil ,  Tim Tri Hoang

IPC: H04L7/00 ,  H03K7/08 ,  H04L7/04

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

公开(公告)号：US11115177B2

公开(公告)日：2021-09-07

申请号：US15868907

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Yanjing Ke ,  Dinesh Patil ,  Tim Tri Hoang

IPC: H04L7/00 ,  H04L7/04 ,  H03K7/08 ,  H03K5/156

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.