公开(公告)号：US20240031308A1

公开(公告)日：2024-01-25

申请号：US18478755

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ashish Gupta ,  Keong Hong Oh ,  Gia Thuyet Ngo ,  Vikrant Kapila ,  Ankita Roy

IPC: H04L49/109

CPC classification number: H04L49/109

Abstract: An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.