公开(公告)号：US20230282724A1

公开(公告)日：2023-09-07

申请号：US17687038

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Tsuan-Chung Chang ,  Charles H. Wallace ,  Peter P. Sun ,  Tahir Ghani ,  Virupaxi Goornavar

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L21/823481 ,  H01L29/78696

Abstract: Techniques are provided herein to form an integrated circuit having gate cut structures or plug structures between source or drain regions, with an angled cut made to the top portion of the structures. In an example, a semiconductor device includes a semiconductor region extending between source and drain regions, and a gate structure extending over the semiconductor region. A gate cut structure is present adjacent to the semiconductor device and interrupts the gate structure. The gate cut structure has a first width along a first plane that extends through the semiconductor region and a second width along a second plane parallel to the first plane and above the semiconductor region, where the first width is greater than the second width. Similar angled plug structures may be provided adjacent to the source and drain regions to increase the landing area made to the metal contacts on the source and drain regions.