公开(公告)号：US20230282724A1

公开(公告)日：2023-09-07

申请号：US17687038

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Tsuan-Chung Chang ,  Charles H. Wallace ,  Peter P. Sun ,  Tahir Ghani ,  Virupaxi Goornavar

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L21/823481 ,  H01L29/78696

Abstract: Techniques are provided herein to form an integrated circuit having gate cut structures or plug structures between source or drain regions, with an angled cut made to the top portion of the structures. In an example, a semiconductor device includes a semiconductor region extending between source and drain regions, and a gate structure extending over the semiconductor region. A gate cut structure is present adjacent to the semiconductor device and interrupts the gate structure. The gate cut structure has a first width along a first plane that extends through the semiconductor region and a second width along a second plane parallel to the first plane and above the semiconductor region, where the first width is greater than the second width. Similar angled plug structures may be provided adjacent to the source and drain regions to increase the landing area made to the metal contacts on the source and drain regions.

公开(公告)号：US20220413376A1

公开(公告)日：2022-12-29

申请号：US17358446

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Tahir Ghani ,  Charles Wallace ,  Hossam Abdallah ,  Dario Farias ,  Tsuan-Chung Chang ,  Chia-Ho Tsai ,  Chetana Singh ,  Desalegne Teweldebrhan ,  Robert Joachim ,  Shengsi Liu

IPC: G03F1/22 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311

Abstract: Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

公开(公告)号：US20230290825A1

公开(公告)日：2023-09-14

申请号：US17693136

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sean Pursel ,  Raghuram Gandikota ,  Sikandar Abbas ,  Tsuan-Chung Chang ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Elliot N. Tan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/66742 ,  H01L27/0886

Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

公开(公告)号：US20230282700A1

公开(公告)日：2023-09-07

申请号：US17685632

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Tsuan-Chung Chang ,  Tahir Ghani ,  Robert Joachim ,  Sean Pursel

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are provided herein to form fin cut structures, or fin isolation structures, after the metal gate has been formed. In an example, a row of semiconductor devices each include a semiconductor region extending in a first direction between a source region and a drain region, and a gate structure extending in a second direction over the semiconductor regions of each neighboring semiconductor device along the row. A fin cut structure that includes a dielectric material interrupts the gate structure and replaces the semiconductor region of one of the semiconductor devices, effectively cutting through the length of the semiconductor device fin (or nanoribbons). The gate structure is formed first followed by removing a portion of the gate structure and removing the semiconductor region of one of the semiconductor devices to form the fin cut structure. In this way, the fin cut structure does not interfere when forming the gate structure.