公开(公告)号：US12278630B2

公开(公告)日：2025-04-15

申请号：US17484463

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Volker Mauer

IPC: G06F17/14 ,  H03K19/0175 ,  H03K19/17728 ,  H03K19/17736

Abstract: A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

公开(公告)号：US20230128025A1

公开(公告)日：2023-04-27

申请号：US18145002

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Volker Mauer

IPC: G06F7/02

Abstract: Circuitry, systems, and methods are provided for an integrated circuit that includes digital filter circuitry. The digital filtering circuitry includes a first partial filter that includes a first number of taps corresponding to coefficients of a first bit depth and a second partial filter that includes a second number of taps corresponding to coefficients of a second bit depth.

公开(公告)号：US20230096355A1

公开(公告)日：2023-03-30

申请号：US18076831

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Volker Mauer

IPC: H04B15/00 ,  H04L27/26

Abstract: An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.

公开(公告)号：US20220014199A1

公开(公告)日：2022-01-13

申请号：US17484463

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Volker Mauer

IPC: H03K19/17728 ,  H03K19/0175 ,  G06F17/14 ,  H03K19/17736

Abstract: A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.