-
公开(公告)号：US20190163639A1
公开(公告)日：2019-05-30
申请号：US16264615
申请日：2019-01-31
Applicant: Intel Corporation
IPC: G06F12/0888
Abstract: An apparatus is described. The apparatus includes memory controller logic circuitry to interface to a multi-level memory having a higher memory level to act as a memory side cache for a lower memory level. The memory controller logic circuitry having policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.
Search Results
1
records
(took 0.009 seconds)
筛选
AND
AND
过滤
NOT
NOT
Scan to Join
