公开(公告)号：US20200026655A1

公开(公告)日：2020-01-23

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0873 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/02 ,  G06F13/16

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

公开(公告)号：US20180285274A1

公开(公告)日：2018-10-04

申请号：US15476838

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Elvira TERAN ,  Zeshan A. CHISHTI ,  Christopher B. WILKERSON ,  Zhe WANG

IPC: G06F12/0864 ,  G06F12/0804 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06

Abstract: Provided are an apparatus, method, and system for just-in-time cache associativity for a cache memory having cache locations as a cache for a non-volatile memory. Data is received for a target address in the non-volatile memory to add to the cache memory. A determination is made of a direct mapped cache location in the cache memory from the a target address in the non-volatile memory. The data for the target address at an available cache location in the cache memory different from the direct mapped cache location is written in response to the direct mapped cache location storing data for another address in the non-volatile memory. The data for the target address in the direct mapped cache location is written in response to the direct mapped cache location not storing data for another address in the non-volatile memory.

公开(公告)号：US20170277633A1

公开(公告)日：2017-09-28

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zhe WANG ,  Zeshan A. CHISHTI

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US20230101512A1

公开(公告)日：2023-03-30

申请号：US17485372

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Christopher HUGHES ,  Zhe WANG ,  Dan BAUM ,  Alexander HEINECKE ,  Evangelos GEORGANAS ,  Lingxiang XIANG ,  Joseph NUZMAN ,  Ritu GUPTA

IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0811

Abstract: Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

公开(公告)号：US20190163639A1

公开(公告)日：2019-05-30

申请号：US16264615

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Wei A. WU ,  Zhe WANG

IPC: G06F12/0888

Abstract: An apparatus is described. The apparatus includes memory controller logic circuitry to interface to a multi-level memory having a higher memory level to act as a memory side cache for a lower memory level. The memory controller logic circuitry having policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.

公开(公告)号：US20190163628A1

公开(公告)日：2019-05-30

申请号：US16262691

申请日：2019-01-30

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN

IPC: G06F12/0804

Abstract: An apparatus is described. The apparatus includes memory control logic circuitry having circuity to a limit an amount of dirty data kept in a volatile level of a multi-level memory. The volatile level of the multi-level memory to act as a cache for a non-volatile, lower level of the multi-level memory. The amount of dirty data in the cache to be limited by the memory control logic circuitry to less than the capacity of the cache.

公开(公告)号：US20180188953A1

公开(公告)日：2018-07-05

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Zeshan A. CHISHTI ,  Muthukumar P. SWAMINATHAN ,  Alaa R. ALAMELDEEN ,  Kunal A. KHOCHARE ,  Jason A. GAYMAN

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3418

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US20180188797A1

公开(公告)日：2018-07-05

申请号：US15394631

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus is described. The apparatus includes power management logic circuitry to implement a power management scheme for a link in which a prior history of the link's idle time behavior is used to determine a first estimate of the link's power consumption while idle in a higher power state and determine a second estimate of the link's power consumption while idle in a lower power state. The first and second estimates are used to determine an idle time for the link at which the link is transitioned to the lower power state.

公开(公告)号：US20200042343A1

公开(公告)日：2020-02-06

申请号：US16586859

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Andrew V. ANDERSON ,  Alaa R. ALAMELDEEN ,  Andrew M. RUDOFF

IPC: G06F9/455

Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

公开(公告)号：US20190179764A1

公开(公告)日：2019-06-13

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN ,  Lidia WARNES ,  Andy M. RUDOFF ,  Muthukumar P. SWAMINATHAN

IPC: G06F12/0891 ,  G06F12/0893 ,  G06F12/02

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.