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公开(公告)号：US10673461B2
公开(公告)日：2020-06-02
申请号：US15778239
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Chia-Hsiang Chen , Wei Tang , Farhana Sheikh
Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.
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