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公开(公告)号：US10673461B2
公开(公告)日：2020-06-02
申请号：US15778239
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Chia-Hsiang Chen , Wei Tang , Farhana Sheikh
Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.
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公开(公告)号：US10193683B2
公开(公告)日：2019-01-29
申请号：US15214531
申请日：2016-07-20
Applicant: Intel Corporation
Inventor： Chia-Hsiang Chen , Ching-En Lee , Feng Xue , Shu-Ping Yeh
Abstract: A communication circuit arrangement includes a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to an input signal for an amplifier to obtain an estimated interference signal, a cancelation circuit configured to subtract the estimated interference signal from a received signal to obtain a clean signal, and a filter update circuit configured to alternate between updating the kernel dimension filter and the delay tap dimension filter using the clean signal.
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公开(公告)号：US09935615B2
公开(公告)日：2018-04-03
申请号：US14861421
申请日：2015-09-22
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Ching-En Lee , Feng Xue , Anuja S. Vaidya , Eduardo X. Alban , Albert Oskar Filip Andersson , Chia-Hsiang Chen , Shu-Ping Yeh
CPC classification number: H03H21/0012 , G06F9/3877 , G06F17/16 , H03H2021/0049 , H03H2021/0094 , H03H2218/06 , H04B1/525
Abstract: An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.
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公开(公告)号：US20170085252A1
公开(公告)日：2017-03-23
申请号：US14861421
申请日：2015-09-22
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Ching-En Lee , Feng Xue , Anuja S. Vaidya , Eduardo X. Alban , Albert Oskar Filip Andersson , Chia-Hsiang Chen , Shu-Ping Yeh
CPC classification number: H03H21/0012 , G06F9/3877 , G06F17/16 , H03H2021/0049 , H03H2021/0094 , H03H2218/06 , H04B1/525
Abstract: An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.
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