公开(公告)号：US20230096585A1

公开(公告)日：2023-03-30

申请号：US18075183

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Yanjing Ke ,  Yew Fatt Kok

IPC: G06F13/40

Abstract: The present disclosure is directed to improving compatibility between chiplets integrated with disparate chiplet interfaces. To reduce compatibility issues due non-matching bump maps, a dual-mode bump map assignment may be implemented to enable a chiplet to utilize multiple signal number sequence assignments. Additionally, a modularized Advanced Interface Bus (AIB) interface may be implemented to reduce channel mismatch in AIB -UCIe multi-channel interoperability.

公开(公告)号：US20220390694A1

公开(公告)日：2022-12-08

申请号：US17338928

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Thu Ngoc Tran ,  Yew Fatt Kok ,  Kumar Abhishek Singh ,  Xiaoqian Li ,  Marely Tejeda Ferrari ,  Ravindranath Mahajan ,  Kevin Ma ,  Casey Thielen

IPC: G02B6/42

Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.