公开(公告)号：US20240402442A1

公开(公告)日：2024-12-05

申请号：US18326458

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaoqian Li ,  Kaveh Hosseini ,  Tim T. Hoang

IPC: G02B6/42

Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.

公开(公告)号：US20240329301A1

公开(公告)日：2024-10-03

申请号：US18130052

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Ravindranath V. Mahajan ,  Chia-Pin Chiu

IPC: G02B6/12

CPC classification number: G02B6/12004

Abstract: A substrate for a multi-chip package includes at least one photonic integrated circuit (PIC) interposer mounted in a cavity in a first major surface. Each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. The substrate further includes at least one optical coupler that is optically coupled to the PIC interposer.

公开(公告)号：US20240319437A1

公开(公告)日：2024-09-26

申请号：US18189844

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Julia Chiu ,  Chia-Pin Chiu ,  Kaveh Hosseini ,  Madhubanti Chatterjee

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/136

Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.

公开(公告)号：US20230341638A1

公开(公告)日：2023-10-26

申请号：US17725018

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Omkar G. Karhade ,  Kaveh Hosseini

IPC: G02B6/42

CPC classification number: G02B6/4212 ,  G02B6/428 ,  G02B6/4273 ,  G02B6/4206

Abstract: Variations in a thermal structure for an open cavity photonic integrated circuit (OCPIC) having an MRR. The structure includes an air trench in fluid communication with an air cavity that is located under the MRR. The air trench is a gap/opening in the oxide that encircles at least a portion of the MRR and extends outward radially therefrom, with a consistent width, to a diameter D1. An oxide cladding is not removed in areas that are used for metal traces and routing. The structure is characterized by straight walls along the air trench. The structure has a lower diameter D2, measured at a bottom/floor of the air cavity. In various embodiments, D2 is substantially equal to D1.

公开(公告)号：US20230194791A1

公开(公告)日：2023-06-22

申请号：US17557630

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar Karhade ,  Kaveh Hosseini ,  Chia-Pin Chiu

IPC: G02B6/36 ,  G02B3/00 ,  H01L25/16

CPC classification number: G02B6/3616 ,  G02B3/0087 ,  H01L25/167 ,  G02B2003/0093

Abstract: An electronic device may include a photonic integrated circuit (PIC) coupled with a substrate. The PIC may communicate a photonic signal with one or more optical fibers. The PIC may process the photonic signal into an electronic signal. The electronic device may include an electronic integrated circuit (EIC) coupled with the substrate. The EIC may communicate with the PIC. The EIC may transmit the electronic signal to the PIC. The EIC may receive the electronic signal from the PIC. The electronic device may include a lens assembly. The lens assembly may include at least one gradient refractive index (GRIN) lens.

公开(公告)号：US20250110270A1

公开(公告)日：2025-04-03

申请号：US18478871

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/12

Abstract: The substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. The multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (PIC) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second PIC die. The integrated circuit component further includes a first intermediate waveguide optically coupling a first PIC waveguide of the first PIC die to a first substrate waveguide in the substrate, and a second intermediate waveguide optically coupling a second PIC waveguide of the second PIC die to a second substrate waveguide in the substrate. The integrated circuit component may further include a third intermediate waveguide optically coupling the first PIC die to the second PIC die.

公开(公告)号：US20240319457A1

公开(公告)日：2024-09-26

申请号：US18189911

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/42

CPC classification number: G02B6/4273 ,  G02B6/4238 ,  G02B6/4274

Abstract: In one embodiment, a photonic integrated circuit (PIC) device includes conductive pads on a surface of the PIC and a micro ring resonator (MRR) with a heater element centrally located between the conductive pads. The PIC also includes a cavity defined within a substrate of the PIC below the MRR, and a plurality of holes defined between the MRR and the conductive pads. The holes extend from a top surface of the PIC into the cavity, and each hole is between a respective conductive pad and the MRR.

公开(公告)号：US12282174B2

公开(公告)日：2025-04-22

申请号：US17131714

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Conor O'Keeffe ,  Brandon C. Marin ,  Hiroki Tanaka

IPC: G02B27/28 ,  F21V8/00 ,  G02B6/10 ,  G02B6/27

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a dual polarization chiplet that may be used by an optical receiver to split multi-polarized light traveling on a single fiber and carrying two or more light signals into two or more fibers each carrying the particular light signal. The dual polarization chiplet may also be used by an optical transmitter to combine multiple light signals to be transmitted onto a single fiber, where each of the multiple light signals are represented by a different polarization of a wavelength on the single fiber. Other embodiments may be described and/or claimed.

公开(公告)号：US20250110294A1

公开(公告)日：2025-04-03

申请号：US18479012

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/42

Abstract: Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator beam underneath it, causing the actuator beam and the waveguides to be deflected. In this manner, the waveguides in the optical interposer can be positioned to align to waveguides in the PIC die.

公开(公告)号：US12158625B2

公开(公告)日：2024-12-03

申请号：US17132967

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Xiaoqian Li ,  Conor O'Keeffe ,  Jing Fang ,  Kevin P. Ma ,  Shamsul Abedin

IPC: G02B6/42 ,  H01L21/66

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a bidirectional optical grating coupler that may be used for testing. A photonic apparatus includes a first layer with electro-optical circuitry that is optically coupled with a bidirectional optical grating coupler. A second layer is physically coupled with a first side of the first layer and includes a first light path to optically coupled with the bidirectional optical grating coupler. A third layer is physically coupled with a second side of the first layer opposite the first side of the first layer, and includes a second light path that optically couples with the bidirectional grating coupler. Operational testing of the electro-optical circuitry is based in part on light received or transmitted through the second light path. Other embodiments may be described and/or claimed.