公开(公告)号：US20230139346A1

公开(公告)日：2023-05-04

申请号：US17549685

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Liu LIU ,  Junchao DING ,  Yingming LIU ,  Jong Sun SEL ,  Yixin MA ,  Jinwoo LEE ,  Xi LIN

IPC: G11C16/04 ,  G11C8/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.