公开(公告)号：US20230139346A1

公开(公告)日：2023-05-04

申请号：US17549685

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Liu LIU ,  Junchao DING ,  Yingming LIU ,  Jong Sun SEL ,  Yixin MA ,  Jinwoo LEE ,  Xi LIN

IPC: G11C16/04 ,  G11C8/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

公开(公告)号：US20230036595A1

公开(公告)日：2023-02-02

申请号：US17791176

申请日：2020-02-08

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Brian J. CLEEREMAN ,  Srivardhan GOWDA ,  Jui-Yen LIN ,  Liu LIU ,  Krishna PARAT ,  Jong Sun SEL ,  Baosuo ZHOU

IPC: H01L27/11582 ,  H01L27/11575 ,  G11C16/08

Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.