公开(公告)号：US20230409478A1

公开(公告)日：2023-12-21

申请号：US18241458

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Kermin CHOFLEMING ,  Yu BAI ,  Simon C. STEELY, JR.

IPC: G06F12/0811 ,  G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/0292 ,  G06F2212/1021

Abstract: Latency on the miss path to a cache level in a CPU module is reduced by predicting when a cache miss is likely. Main memory is directly accessed in parallel with the access to the cache level in the CPU module based on the prediction that a cache miss is likely in the cache level.

公开(公告)号：US20220283948A1

公开(公告)日：2022-09-08

申请号：US17751049

申请日：2022-05-23

Applicant: Intel Corporation

Inventor： Kermin CHOFLEMING ,  Yu BAI

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F12/126

Abstract: An example of a system using two-stage, the cache tag is stored in a primary and a secondary tag memories. When requesting data, the system searches the cache to retrieve the data, an operation that involves cache tag lookup. Cache tag lookup is performed by cache management. The cache management receives a cache tag for reading data from the cache memory. The cache management selects a hash function from a group of hash functions and computes a primary lookup tag using the selected hash function and the cache tag. The cache management compares the primary lookup tag to the contents of the primary tag memory to determine if there is a hit. If there is no hit, the cache management selects another hash function and repeats the search in the primary tag memory.