公开(公告)号：US20230409478A1

公开(公告)日：2023-12-21

申请号：US18241458

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Kermin CHOFLEMING ,  Yu BAI ,  Simon C. STEELY, JR.

IPC: G06F12/0811 ,  G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/0292 ,  G06F2212/1021

Abstract: Latency on the miss path to a cache level in a CPU module is reduced by predicting when a cache miss is likely. Main memory is directly accessed in parallel with the access to the cache level in the CPU module based on the prediction that a cache miss is likely in the cache level.

公开(公告)号：US20220283948A1

公开(公告)日：2022-09-08

申请号：US17751049

申请日：2022-05-23

Applicant: Intel Corporation

Inventor： Kermin CHOFLEMING ,  Yu BAI

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F12/126

Abstract: An example of a system using two-stage, the cache tag is stored in a primary and a secondary tag memories. When requesting data, the system searches the cache to retrieve the data, an operation that involves cache tag lookup. Cache tag lookup is performed by cache management. The cache management receives a cache tag for reading data from the cache memory. The cache management selects a hash function from a group of hash functions and computes a primary lookup tag using the selected hash function and the cache tag. The cache management compares the primary lookup tag to the contents of the primary tag memory to determine if there is a hit. If there is no hit, the cache management selects another hash function and repeats the search in the primary tag memory.

公开(公告)号：US20220107897A1

公开(公告)日：2022-04-07

申请号：US17552239

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： David KEPPEL ,  Swapna RAJ ,  Kermin CHOFLEMING ,  Samantika S. SURY

IPC: G06F12/0842

Abstract: Examples described herein relate to circuitry to selectively disable cache snoop operations issued by a particular processor or its cache manager based on data in a memory address range, to be accessed by the particular processor, having been flushed from one or more other cache devices accessible to other processors. At or after completion of flushing or scrubbing data in the memory address range to memory, the particular processor or its cache manager do not issue snoop operations for accesses to the memory address range. In response to an access by some other device to the memory address range, the processor or cache manager may resume issuing snoop operations.

公开(公告)号：US20210224213A1

公开(公告)日：2021-07-22

申请号：US17206961

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Swapna RAJ ,  Samantika S. SURY ,  Kermin CHOFLEMING ,  Simon C. STEELY, JR.

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/0815

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.