公开(公告)号：US20180183899A1

公开(公告)日：2018-06-28

申请号：US15853624

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Nausheen ANSARI ,  Srikanth KAMBHATLA ,  Abdul R. ISMAIL ,  Karthi R. VADIVELU ,  John S. HOWARD ,  Gal YEDIDIA ,  Reuven ROZIC ,  Paul S. DIEFENBAUGH ,  Zachary F. HAMM

IPC: H04L29/06 ,  G09G3/20

CPC classification number: H04L69/03 ,  G09G3/2096 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2370/042 ,  G09G2370/047 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16 ,  H04L69/24 ,  H04N21/242 ,  H04N21/43635 ,  H04N21/8547

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may be operable to provide output to a unidirectional data path for carrying a packetized data stream. The second circuitry may be operable to provide output to, and obtain input from, a bidirectional control path for carrying a packetized control stream. The packetized data stream may comprise pixel data traffic and frame-synchronous metadata traffic, and the packetized control stream may comprise frame-asynchronous metadata traffic and control traffic.