公开(公告)号：US20180018243A1

公开(公告)日：2018-01-18

申请号：US15611625

申请日：2017-06-01

Applicant: Intel IP Corporation

Inventor： Florian ECKARDT ,  Zhibin YU ,  Qing XU

IPC: G06F11/18 ,  G06F11/14 ,  H03M13/25 ,  H03M13/41

CPC classification number: G06F11/18 ,  G06F11/1479 ,  H03M13/256 ,  H03M13/3994 ,  H03M13/41 ,  H04L1/0054

Abstract: The disclosure relates to a decoding device, comprising: a receiver configured to provide a sequence of information bits comprising context redundancy information, wherein the sequence of information bits is encoded based on a predefined channel code; a trellis generation logic configured to generate a plurality of trellis states based on the sequence of information bits and the channel code; a trellis reduction logic configured to reduce the plurality of trellis states by at least one trellis state based on the context redundancy information; and a decoder configured to decode the sequence of information bits by using a metric based on the reduced number of trellis states.