公开(公告)号：US20210281253A1

公开(公告)日：2021-09-09

申请号：US16474564

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Michael Kalcher ,  Daniel Gruber ,  Francesco Conzatti ,  Patrizia Greco

IPC: H03K5/00

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

公开(公告)号：US11323102B2

公开(公告)日：2022-05-03

申请号：US16474564

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Michael Kalcher ,  Daniel Gruber ,  Francesco Conzatti ,  Patrizia Greco

IPC: H03K5/00

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

公开(公告)号：US10651869B1

公开(公告)日：2020-05-12

申请号：US16364891

申请日：2019-03-26

Applicant: Intel IP Corporation ,  Intel Corporation

Inventor： Davide Ponton ,  Michael Kalcher ,  Alan Paussa ,  Edwin Thaller ,  Franz Kuttner ,  Daniel Gruber

IPC: H03M1/48 ,  H03M1/66 ,  H04B1/403 ,  H04B1/401 ,  H04B1/04

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.