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公开(公告)号：US10651869B1
公开(公告)日：2020-05-12
申请号：US16364891
申请日：2019-03-26
Applicant: Intel IP Corporation , Intel Corporation
Inventor： Davide Ponton , Michael Kalcher , Alan Paussa , Edwin Thaller , Franz Kuttner , Daniel Gruber
Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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公开(公告)号：US11323102B2
公开(公告)日：2022-05-03
申请号：US16474564
申请日：2017-03-29
Applicant: Intel IP Corporation
Inventor： Michael Kalcher , Daniel Gruber , Francesco Conzatti , Patrizia Greco
IPC: H03K5/00
Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.
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公开(公告)号：US20210281253A1
公开(公告)日：2021-09-09
申请号：US16474564
申请日：2017-03-29
Applicant: Intel IP Corporation
Inventor： Michael Kalcher , Daniel Gruber , Francesco Conzatti , Patrizia Greco
IPC: H03K5/00
Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.
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公开(公告)号：US09900016B1
公开(公告)日：2018-02-20
申请号：US15588065
申请日：2017-05-05
Applicant: INTEL IP CORPORATION
Inventor： Stefan Trampitsch , Daniel Gruber
CPC classification number: H03M1/0602 , H03M1/0845 , H03M1/66
Abstract: An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).
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公开(公告)号：US11962320B2
公开(公告)日：2024-04-16
申请号：US17753917
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Albert Molina , Hundo Shin
CPC classification number: H03M1/1071 , G01R31/2856 , G01R31/3187 , G01R31/26 , H03M1/0854 , H03M1/462
Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.
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Patent Agency Ranking
公开(公告)号：US20210409065A1
公开(公告)日：2021-12-30
申请号：US16912741
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , L. Mark Elzinga , Martin Clara
Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
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公开(公告)号：US11171663B2
公开(公告)日：2021-11-09
申请号：US16833729
申请日：2020-03-30
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US10715185B1
公开(公告)日：2020-07-14
申请号：US16369317
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US10608661B1
公开(公告)日：2020-03-31
申请号：US16369262
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US12273120B2
公开(公告)日：2025-04-08
申请号：US17358084
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Martin Clara , Daniel Gruber , Christian Lindholm , Michael Fulde , Giacomo Cascio
Abstract: An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M
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