公开(公告)号：US10733032B2

公开(公告)日：2020-08-04

申请号：US15685506

申请日：2017-08-24

申请人： International Business Machines Corporation

发明人： John Divirgilio ,  Liana L. Fong ,  John Lewars ,  Seetharami R. Seelam ,  Brian F. Veale

IPC分类号： G06F9/54 ,  G06F9/38 ,  G06F9/48

摘要： A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

公开(公告)号：US20200073721A1

公开(公告)日：2020-03-05

申请号：US16117025

申请日：2018-08-30

申请人： International Business Machines Corporation

发明人： Brian F. Veale ,  Bruce Mealey ,  Andre L. Albot ,  Nick Stilwell

IPC分类号： G06F9/50 ,  G06F9/48

摘要： A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.

公开(公告)号：US11061733B2

公开(公告)日：2021-07-13

申请号：US16117025

申请日：2018-08-30

申请人： International Business Machines Corporation

发明人： Brian F. Veale ,  Bruce Mealey ,  Andre L. Albot ,  Nick Stilwell

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/48

摘要： A digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.

公开(公告)号：US09836334B2

公开(公告)日：2017-12-05

申请号：US13914893

申请日：2013-06-11

申请人： International Business Machines Corporation

发明人： John Divirgilio ,  Liana L. Fong ,  John Lewars ,  Seetharami R. Seelam ,  Brian F. Veale

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/54

CPC分类号： G06F9/542 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4812 ,  G06F9/4818

摘要： A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

公开(公告)号：US11663312B2

公开(公告)日：2023-05-30

申请号：US16131982

申请日：2018-09-14

申请人： International Business Machines Corporation

发明人： Brian F. Veale ,  Bruce Mealey ,  Andre L. Albot ,  Nick Stilwell

IPC分类号： G06F21/44 ,  G06F13/40

CPC分类号： G06F21/44 ,  G06F13/4022

摘要： Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.

公开(公告)号：US20200089865A1

公开(公告)日：2020-03-19

申请号：US16131982

申请日：2018-09-14

申请人： International Business Machines Corporation

发明人： Brian F. Veale ,  Bruce Mealey ,  Andre L. Albot ,  Nick Stilwell

IPC分类号： G06F21/44 ,  G06F13/40

摘要： Accelerator access control whereby an application's access to an accelerator is revoked in order to allow the system to perform a system function. In one or more embodiments, when an application is executing, a credit system is utilized to provide credits for controlled access to the accelerator. When request information is received to remove access to a credit associated with the application's access to the accelerator, the credit is marked to fail with operating system interfaces. Also, in one or more embodiments, if the credit is in use for accessing the accelerator, an effective address associated with the credit is unmapped from the accelerator.