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公开(公告)号:US10943051B1
公开(公告)日:2021-03-09
申请号:US16565851
申请日:2019-09-10
发明人: Jesse Surprise , Gerald Strevig, III , Shawn Kollesar , Chris Aaron Cavitt , Chaobo Li , Dina Hamid , Christopher Berry
IPC分类号: G06F30/398 , G06F30/33 , G06F30/394 , H01L23/522
摘要: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.
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公开(公告)号:US20210073348A1
公开(公告)日:2021-03-11
申请号:US16565851
申请日:2019-09-10
发明人: Jesse SURPRISE , Gerald Strevig, III , Shawn Kollesar , Chris Aaron Cavitt , Chaobo Li , Dina Hamid , Christopher Berry
IPC分类号: G06F17/50 , H01L23/522
摘要: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.
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公开(公告)号:US10831954B1
公开(公告)日:2020-11-10
申请号:US16667880
申请日:2019-10-29
发明人: Debjit Sinha , Ravi Chander Ledalla , Chaobo Li , Adil Bhanji , Gregory Schaeffer , Michael Hemsley Wood
IPC分类号: G06F17/50 , G06F30/30 , G06F30/398 , G06F30/3312 , G06F30/3323 , G06F30/373 , G06F30/337
摘要: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.
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